The present invention relates to computer technologies, and more particularly, to memory systems for computers.
Modern computer architectures typically provide one or more multi-core processors connected to a tiered memory structure that includes various levels of caches and a main memory. As a processor executes application code that is part of an instruction stream, the processor must continually retrieve instructions and data from the tiered memory structure for processing. If a faster, proximally closer memory, such as a Level 1 cache, does not contain the necessary instructions or data required by the processor, the processor must typically wait for a slower, more distant memory, such as a Level 2 or 3 cache or a main memory, to provide the information.
Such architectures are inefficient to the extent that significant time and energy are consumed to move information between the processor cores and the tiered memory structure. For example, if a closer memory does not contain the necessary instructions or data required by the processor, depending on the distance between the processor and the memory containing the required information, the computer system could suffer from significantly greater access latencies and power consumed simply by transferring bits between circuits than would otherwise be necessary.
One approach toward mitigating access latency is to provide a three-dimensional (3D) memory with a helper processor as described in U.S. patent application Ser. No. 13/567,958, titled “Stacked Memory Device with Helper Processor.” In this approach, layers of memory are stacked and connected through the use of “through-silicon vias” (TSV's) and a helper processor is provided to perform certain memory-intensive operations. Although this approach provides some improvement with respect to speed and bandwidth, it continues to rely on a conventional approach of linearly organizing instructions and data.
A need therefore exists to provide an improved architecture capable of meeting increasing performance demands while improving access latencies with minimized power consumptions.